View LC75805PE_8977386.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor component s industries, llc, 2017 1 publication order number : june 2017 - rev. 2 LC75805PE/d www.onsemi.com ordering information see detailed ordering and shipping info rmation on page 34 of this data sheet. * computer control bus (ccb) is an on semiconductor?s original bus format and the bus addresses are controlled by on semiconductor. LC75805PE 1/1 to 1/4 duty general-purpose lcd driver with led driver overview LC75805PE is the 1/1 to 1/4 duty general-purpose lcd display driver with the led driver to use for the instrument panel display by control with the controller. in addition, LC75805PE is able to drive up to 48 led and lcd of up to 140 segments directly, and has a built-in 7ch pwm function for brightness adjustment of le d. furthermore, because of built-in the oscillator circuit, it is possible to reduce external resister and capacitor for oscillation. features ? switch of static drive, 1/2 duty drive, 1/3 duty drive and 1/4 duty drive can be controlled by serial data. static drive (1/1 duty drive) : capable of driving up to 38 segments. 1/2 duty drive : capable of driving up to 74 segments. 1/3 duty drive : capable of driving up to 108 segments. 1/4 duty drive : capable of driving up to 140 segments. ? frame frequency of common and segment output waveform can be controlled by serial data. ? turning on/off led can be controlled by serial data. (capable of driving up to 48 led) ? built-in 7 ch pwm function for brightness adjustment of led. (resolution of 128 steps) ? frame frequency of led driver output waveform can be controlled by serial data. ? serial data input supports ccb* format communication with the system controller. (support 5 v operation) ? backup function and forced turning off all segments by power-saving mode can be controlled by serial data. ? switch of the internal oscillator operating mode and the external clock operating mode can be controlled by serial data. ? high generality, since display data is displayed directly without the intervention of a decoder circuit. ? the inh pin allows the display to be forced to the off state. ? built-in oscillator circuit (built-in resister and capacitor for oscillation) pqfp100 14x20 / qip100e
LC75805PE www.onsemi.com 2 specifications absolute maximum ratings at ta = 25 ? c, v ss = 0 v parameter symbol conditions ratings unit maximum supply voltage v dd max v dd ? 0.3 to +6.5 v input voltage v in 1 ce, cl, di, inh , osci ? 0.3 to +6.5 v output voltage v out 1 s1 to s38, com1 to com4 ? 0.3 to v dd +0.3 v v out 2 ld1 to ld48 ? 0.3 to +35 output current i out 1 s1 to s38 300 ? a i out 2 com1 to com4 3 ma i out 3 ld1 to ld48 30 allowable power dissipation pd max ta = 95 ? c 400 mw operating temperature topr ? 40 to +95 ? c storage temperature tstg ? 55 to +150 ? c allowable operating ranges at ta = ? 40 to +95 ? c, v ss = 0 v parameter symbol conditions ratings unit min typ max supply voltage v dd v dd 4.5 5.5 v input high-level voltage v ih 1 ce, cl, di, inh 0.8v dd 5.5 v v ih 2 osci 0.8v dd 5.5 input low-level voltage v il 1 ce, cl, di, inh 0 0.2v dd v v il 2 osci 0 0.2v dd output pull-up voltage v oup ld1 to ld48, v dd = 4.5 to 5.5 v 0 30 v external clock operating frequency f ck osci, external clock operating mode [fig 3] 100 300 600 khz external clock duty d ck osci, external clock operating mode [fig 3] 30 50 70 % data setup time tds cl, di [fig 1], [fig 2] 160 ns data hold time tdh cl, di [fig 1], [fig 2] 160 ns ce wait time tcp ce, cl [fig 1], [fig 2] 160 ns ce setup time tcs ce, cl [fig 1], [fig 2] 160 ns ce hold time tch ce, cl [fig 1], [fig 2] 160 ns high-level clock pulse width t ? h cl [fig 1], [fig 2] 160 ns low-level clock pulse width t ? l cl [fig 1], [fig 2] 160 ns rise time tr ce, cl, di [fig 1], [fig 2] 160 ns fall time tf ce, cl, di [fig 1], [fig 2] 160 ns inh switching time tc inh , ce [fig 4], [fig 5], [fig 6], [fig 7] 10 ? s functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility. stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected.
LC75805PE www.onsemi.com 3 electrical characteristics for the allowable operating ranges parameter symbol pin conditions ratings unit min typ max hysteresis v h ce, cl, di, inh 0.1v dd v input high-level current i ih 1 ce, cl, di, inh v i = 5.5 v 5.0 ? a i ih 2 osci v i = 5.5 v 5.0 input low-level current i il 1 ce, cl, di, inh v i = 0 v ? 5.0 ? a i il 2 osci v i = 0 v ? 5.0 output off leak current i offh ld1 to ld48 v o = 30 v 5.0 ? a output high-level voltage v oh 1 s1 to s38 i o = ? 20 ? a v dd ? 0.9 v v oh 2 com1 to com4 i o = ? 100 ? a v dd ? 0.9 output low-level voltage v ol 1 s1 to s38 i o = 20 ? a 0.9 v v ol 2 com1 to com4 i o = 100 ? a 0.9 v ol 3 ld1 to ld48 i o = 20 ma 0.25 0.5 output middle-level voltage v mid 1 s1 to s36 1/3 bias i o = 20 ? a 2/3v dd ? 0.9 2/3v dd +0.9 v v mid 2 s1 to s36 1/3 bias i o = 20 ? a 1/3v dd ? 0.9 1/3v dd +0.9 v mid 3 com1 to com4 1/3 bias i o = 100 ? a 2/3v dd ? 0.9 2/3v dd +0.9 v mid 4 com1 to com4 1/3 bias i o = 100 ? a 1/3v dd ? 0.9 1/3v dd +0.9 v mid 5 com1, com2 1/2 bias i o = 100 ? a 1/2v dd ? 0.9 1/2v dd +0.9 oscillator frequency fosc oscillator circuit internal oscillator operating mode 240 300 360 khz current drain i dd 1 v dd power save mode 15 ? a i dd 2 v dd v dd = 5.5 v output open, internal oscillator operating mode 750 1500 i dd 3 v dd v dd = 5.5 v output open, external clock operating mode f ck = 300 khz v ih 2 = 0.9v dd v il 2 = 0.1v dd 750 1500 * electrical characteristics might be c hanged for the improvement without notice. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions.
LC75805PE www.onsemi.com 4 1. when cl is stopped at the low level. [fig 1] 2. when cl is stopped at the high level. [fig 2] 3. osci pin clock timing in external clock operating mode. [fig 3] osci t ck l t ck h f ck = 1 t ck h + t ck l [khz] d ck = t ck h t ck h + t ck l ? 100[%] v il 2 50% v ih 2 tds v il 1 v il 1 v il 1 v ih 1 50% v ih 1 v ih 1 tch tcs tcp tdh tr tf t ? l t ? h ce cl di ? ? ? ? ? ? ? ? tds v il 1 v il 1 v il 1 v ih 1 v ih 1 50% v ih 1 tch tcs tcp tdh tr tf t ? h t ? l ce cl di ? ? ? ? ? ? ? ?
LC75805PE www.onsemi.com 5 package dimensions unit : mm pqfp100 14x20 / qip100e case 122bv issue a xxxxx = specific device code y = year m = month ddd = additional traceability data generic marking diagram* *this information is generic. please refer to device data sheet for actual part marking. xxxxxxxxx ymddd (unit: mm) 22.30 16.30 0.43 0.65 1.30 soldering footprint* note: the measurements are not to guarantee but for reference only. *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 20.0 ? 0.1 12 0.65 (0.58) 0.13 14.0 ? 0.1 17.2 ? 0.2 23.2 ? 0.2 100 0.3 ? 0.05 0.10 3.0 max (2.7) 0.1 ? 0.1 0 to 10 ? 0.15 0.8 ? 0.2
LC75805PE www.onsemi.com 6 pin assignment top view block diagram s13 s9 s8 s3 v dd ld5 ld11 v ss ld20 ld16 v ss ld36 ld41 s33 s34 ld46 ld47 ld48 v ss com1 com2/s38 com3/s37 com4/s36 s35 s32 s31 s30 s29 s28 s27 s26 s25 s24 s23 s22 s21 s20 s19 s18 s17 s16 s15 s14 ld4 ld10 ld3 ld2 ld1 v ss s12 LC75805PE (qip100e) s11 s10 s7 s6 s4 s5 s2 s1 v ss osci ce inh cl ld32 ld31 ld30 ld29 ld28 di 51 80 50 81 31 100 30 1 ld9 ld8 ld7 ld6 ld15 ld19 ld14 ld13 ld12 ld18 ld17 v ss ld24 ld23 ld22 ld21 ld27 ld26 ld25 ld35 ld34 ld33 v ss ld40 ld39 ld38 ld37 ld45 ld44 ld43 ld42 ld1 ld2 ce cl di com1 com2/s38 com3/s37 com4/s36 v ss v dd inh osci shift register led driver ccb interface clock generator common driver ld48 display register & control register segment driver s35 s34 ld47 lcd drive bias voltage stabilization circuit 2/3v dd 1/3v dd 1/2v dd s1 s2 s3 s4 s5
LC75805PE www.onsemi.com 7 pin functions symbol pin no. function active i/o handling when unused ld1 to ld16 ld17 to ld32 ld33 to ld48 2 to 17 20 to 35 38 to 53 these are led driver output pins that display the display data for led transferred by serial data input, and high- voltage open-drain output pins. (pull-up voltage is 30[v] maximum.) in addition, brightness adjustment of led is possible by pwm function, too. - o open com1 com2/s38 com3/s37 com4/s36 55 56 57 58 these are common driver output pins, and frame frequency is fo [hz]. com2/s38, com3/s37 and com4/s36 are possible to be used as the segment output by control data. - o open s35 to s1 59 to 93 these are segment output pins that displa y the display data for lcd transferred by serial data input. - o open osci 96 this is input pin for the external clock. input the clock whose frequency (f ck ) is between 100 and 600[khz] at external clock operating mode. furthermore, connect to gnd at internal oscillator operating mode. - i gnd ce 98 these are input pins for serial data tr ansfer, and connect to the controller. ce: chip enable cl: synchronized clock di: transfer data h i cl 99 i gnd di 100 - i inh 97 display off control input pin ? inh = low-level (v ss ) ...display forced off ld1 to ld48 = z (high-impedance) com1 = l (v ss ) com2/s38 to com4/s36 = l (v ss ) s1 to s35 = l (v ss ) internal oscillator operation is stopped. external clock input is forbidden. ? inh = high-level (v dd )...display on internal oscillator operation is possible. (at internal oscillator operating mode) external clock input is possible. (at external clock operating mode) however, serial data can be transferred during turn off. l i gnd v dd 94 this is power supply pin. supply the voltage bet ween 4.5v and 5.5v. - - - v ss 1 18 19 36 37 54 95 these are power supply pins. connect to gnd. - - -
LC75805PE www.onsemi.com 8 control data 17 bits ccb address 8 bits display data for lcd 140 bits fixed data 9 bits ccb address 8 bits control data 148 bits control data 49 bits ccb address 8 bits display data for led 48 bits fixed data 12 bits dd 3 bits serial data transfer format 1/4 duty drive (1) when cl is stopped at the low level (note 1) the input of serial data is taken in at the rising edge of cl, and latched at the falling edge of ce. in addition, this ic has the function that counts the number of cl cloc k to receive the correct serial data. that is to say, because it isn?t latched at the falling edge of ce when th e number of the count of cl in each serial data is wrong, receiving wrong serial data can be prevented. (note 2) dd ? ? ? direction data ? ccb address ......................... ?87h? ? d1 to d140 ........................... display data for lcd ? oc ........................................ control data for switch of internal oscillator operating mode and external clock operating mode ? fc0 to fc3 ........................... control data for setting of the frame frequency of common and segment output waveform ? dt0, dt1 ............................. control data for setting of dr ive scheme (setting of 1/1 to 1/4 duty drive scheme) of lcd ? sc ......................................... c ontrol data for turning on/off segments ? bu ........................................ cont rol data for switch of normal mode and power-saving mode ? l1a, l1b, l1c to l48a, ...... control data for ch setti ngs of pwm circuits that adjust brightness of led l48b, l48c ? pf0 to pf3 ............................ control data for setting of the frame frequency of led driver output waveform ? lt1 to lt48 ......................... display data for led ? w10 to w16, w20 to w26, ... pwm data of pwm circuits of led driver output w30 to w36, w40 to w46, w50 to w56, w60 to w66 w70 to w76 b1 b0 d2 d1 1 1 d138 oc 0 di cl ce 1 0 0 0 0 0 1 b3 b2 a1 a0 a3 a2 d139 0 0 0 0 0 bu sc fc2 fc1 1 0 0 fc0 0 fc3 dt0 dt1 d140 d136 d137 d135 d134 d133 b1 b0 l1b l1a 1 1 l46c 0 pf3 1 0 0 l47c 0 0 1 b3 b2 a1 a0 a3 a2 l47a l48b l48a l48c pf2 pf0 0 0 0 0 1 0 1 0 pf1 0 0 0 l47b l45c l46a l46b l45b l45a w65 w64 w54 w52 w56 w55 w60 w63 w61 w76 w75 w71 w70 0 1 1 w66 w62 w72 w73 w74 w53 b1 b0 lt2 lt1 1 1 0... w22 w21 1 0 0 w11 0 0 1 b3 b2 a1 a0 a3 a2 0 w13 w12 w14 w20 w15 w33 w32 w25 w24 w36 w35 w34 w23 w16 w26 w30 w31 w10 0 lt48 lt47 w51 w50 w46 w45 w44 w43 w42 w41 w40 dd 3 bits dd 3 bits
LC75805PE www.onsemi.com 9 control data 17 bits ccb address 8 bits display data for lcd 140 bits fixed data 9 bits ccb address 8 bits control data 148 bits control data 49 bits ccb address 8 bits display data for led 48 bits fixed data 12 bits dd 3 bits (2) when cl is stopped at the high level (note 1) the input of serial data is taken in at the rising edge of cl, and latched at the falling edge of ce. in addition, this ic has the function that counts the number of cl cloc k to receive the correct serial data. that is to say, because it isn?t latched at the falling edge of ce when th e number of the count of cl in each serial data is wrong, receiving wrong serial data can be prevented. (note 2) dd ? ? ? direction data ? ccb address ......................... ?87h? ? d1 to d140 ........................... display data for lcd ? oc ........................................ control data for switch of internal oscillator operating mode and external clock operating mode ? fc0 to fc3 ........................... control data for setting of the frame frequency of common and segment output waveform ? dt0, dt1 ............................. control data for setting of dr ive scheme (setting of 1/1 to 1/4 duty drive scheme) of lcd ? sc ......................................... c ontrol data for turning on/off segments ? bu ........................................ cont rol data for switch of normal mode and power-saving mode ? l1a, l1b, l1c to l48a, ...... control data for ch setti ngs of pwm circuits that adjust brightness of led l48b, l48c ? pf0 to pf3 ............................ control data for setting of the frame frequency of led driver output waveform ? lt1 to lt48 ......................... display data for led ? w10 to w16, w20 to w26, ... pwm data of pwm circuits of led driver output w30 to w36, w40 to w46, w50 to w56, w60 to w66 w70 to w76 b1 b0 d2 d1 1 1 d138 oc 0 di cl ce 1 0 0 0 0 0 1 b3 b2 a1 a0 a3 a2 d139 0 0 0 0 0 bu sc fc2 fc1 1 0 0 fc0 0 fc3 dt0 dt1 d140 d136 d137 d135 d134 d133 b1 b0 l1b l1a 1 1 l46c 0 pf3 1 0 0 l47c 0 0 1 b3 b2 a1 a0 a3 a2 l47a l48b l48a l48c pf2 pf0 0 0 0 0 1 0 1 0 pf1 0 0 0 l47b l45c l46a l46b l45b l45a w65 w64 w54 w52 w56 w55 w60 w63 w61 w76 w75 w71 w70 0 1 1 w66 w62 w72 w73 w74 w53 b1 b0 lt2 lt1 1 1 0... w22 w21 1 0 0 w11 0 0 1 b3 b2 a1 a0 a3 a2 0 w13 w12 w14 w20 w15 w33 w32 w25 w24 w36 w35 w34 w23 w16 w26 w30 w31 w10 0 lt48 lt47 w51 w50 w46 w45 w44 w43 w42 w41 w40 dd 3 bits dd 3 bits
LC75805PE www.onsemi.com 10 control data 17 bits ccb address 8 bits display data for lcd 108 bits fixed data 9 bits ccb address 8 bits control data 148 bits control data 49 bits ccb address 8 bits display data for led 48 bits fixed data 12 bits 1/3 duty drive (1) when cl is stopped at the low level (note 1) the input of serial data is taken in at the rising edge of cl, and latched at the falling edge of ce. in addition, this ic has the function that counts the number of cl cloc k to receive the correct serial data. that is to say, because it isn?t latched at the falling edge of ce when th e number of the count of cl in each serial data is wrong, receiving wrong serial data can be prevented. (note 2) dd ? ? ? direction data ? ccb address ......................... ?87h? ? d1 to d108 ........................... display data for lcd ? oc ........................................ control data for switch of internal oscillator operating mode and external clock operating mode ? fc0 to fc3 ........................... control data for setting of the frame frequency of common and segment output waveform ? dt0, dt1 ............................. control data for setting of dr ive scheme (setting of 1/1 to 1/4 duty drive scheme) of lcd ? sc ......................................... c ontrol data for turning on/off segments ? bu ........................................ cont rol data for switch of normal mode and power-saving mode ? l1a, l1b, l1c to l48a, ...... control data for ch setti ngs of pwm circuits that adjust brightness of led l48b, l48c ? pf0 to pf3 ............................ control data for setting of the frame frequency of led driver output waveform ? lt1 to lt48 ......................... display data for led ? w10 to w16, w20 to w26, ... pwm data of pwm circuits of led driver output w30 to w36, w40 to w46, w50 to w56, w60 to w66 w70 to w76 b1 b0 d2 d1 1 1 d106 oc 0 di cl ce 1 0 0 0 0 0 1 b3 b2 a1 a0 a3 a2 d107 0 0 0 0 0 bu sc fc2 fc1 1 0 0 fc0 0 fc3 dt0 dt1 d108 d104 d105 d103 d102 d101 b1 b0 l1b l1a 1 1 l46c 0 pf3 1 0 0 l47c 0 0 1 b3 b2 a1 a0 a3 a2 l47a l48b l48a l48c pf2 pf0 0 0 0 0 1 0 1 0 pf1 0 0 0 l47b l45c l46a l46b l45b l45a w65 w64 w54 w52 w56 w55 w60 w63 w61 w76 w75 w71 w70 0 1 1 w66 w62 w72 w73 w74 w53 b1 b0 lt2 lt1 1 1 0... w22 w21 1 0 0 w11 0 0 1 b3 b2 a1 a0 a3 a2 0 w13 w12 w14 w20 w15 w33 w32 w25 w24 w36 w35 w34 w23 w16 w26 w30 w31 w10 0 lt48 lt47 w51 w50 w46 w45 w44 w43 w42 w41 w40 dd 3 bits dd 3 bits dd 3 bits
LC75805PE www.onsemi.com 11 control data 17 bits ccb address 8 bits display data for lcd 108 bits dd 3 bits fixed data 9 bits ccb address 8 bits control data 148 bits control data 49 bits ccb address 8 bits display data for led 48 bits fixed data 12 bits dd 3 bits (2) when cl is stopped at the high level (note 1) the input of serial data is taken in at the rising edge of cl, and latched at the falling edge of ce. in addition, this ic has the function that counts the number of cl cloc k to receive the correct serial data. that is to say, because it isn?t latched at the falling edge of ce when th e number of the count of cl in each serial data is wrong, receiving wrong serial data can be prevented. (note 2) dd ? ? ? direction data ? ccb address ......................... ?87h? ? d1 to d108 ........................... display data for lcd ? oc ........................................ control data for switch of internal oscillator operating mode and external clock operating mode ? fc0 to fc3 ........................... control data for setting of the frame frequency of common and segment output waveform ? dt0, dt1 ............................. control data for setting of dr ive scheme (setting of 1/1 to 1/4 duty drive scheme) of lcd ? sc ......................................... c ontrol data for turning on/off segments ? bu ........................................ cont rol data for switch of normal mode and power-saving mode ? l1a, l1b, l1c to l48a, ...... control data for ch setti ngs of pwm circuits that adjust brightness of led l48b, l48c ? pf0 to pf3 ............................ control data for setting of the frame frequency of led driver output waveform ? lt1 to lt48 ......................... display data for led ? w10 to w16, w20 to w26, ... pwm data of pwm circuits of led driver output w30 to w36, w40 to w46, w50 to w56, w60 to w66 w70 to w76 b1 b0 d2 d1 1 1 d106 oc 0 di cl ce 1 0 0 0 0 0 1 b3 b2 a1 a0 a3 a2 d107 0 0 0 0 0 bu sc fc2 fc1 1 0 0 fc0 0 fc3 dt0 dt1 d108 d104 d105 d103 d102 d101 b1 b0 l1b l1a 1 1 l46c 0 pf3 1 0 0 l47c 0 0 1 b3 b2 a1 a0 a3 a2 l47a l48b l48a l48c pf2 pf0 0 0 0 0 1 0 1 0 pf1 0 0 0 l47b l45c l46a l46b l45b l45a w65 w64 w54 w52 w56 w55 w60 w63 w61 w76 w75 w71 w70 0 1 1 w66 w62 w72 w73 w74 w53 b1 b0 lt2 lt1 1 1 0... w22 w21 1 0 0 w11 0 0 1 b3 b2 a1 a0 a3 a2 0 w13 w12 w14 w20 w15 w33 w32 w25 w24 w36 w35 w34 w23 w16 w26 w30 w31 w10 0 lt48 lt47 w51 w50 w46 w45 w44 w43 w42 w41 w40 dd 3 bits
LC75805PE www.onsemi.com 12 control data 19 bits ccb address 8 bits display data for lcd 74 bits dd 3 bits fixed data 9 bits ccb address 8 bits control data 148 bits control data 49 bits ccb address 8 bits display data for led 48 bits fixed data 12 bits dd 3 bits 1/2 duty drive (1) when cl is stopped at the low level (note 1) the input of serial data is taken in at the rising edge of cl, and latched at the falling edge of ce. in addition, this ic has the function that counts the number of cl cloc k to receive the correct serial data. that is to say, because it isn?t latched at the falling edge of ce when th e number of the count of cl in each serial data is wrong, receiving wrong serial data can be prevented. (note 2) dd ? ? ? direction data ? ccb address ......................... ?87h? ? d1 to d74 ............................. di splay data for lcd ? oc ........................................ control data for switch of internal oscillator operating mode and external clock operating mode ? fc0 to fc3 ........................... control data for setting of the frame frequency of common and segment output waveform ? dt0, dt1 ............................. control data for setting of dr ive scheme (setting of 1/1 to 1/4 duty drive scheme) of lcd ? sc ......................................... c ontrol data for turning on/off segments ? bu ........................................ cont rol data for switch of normal mode and power-saving mode ? l1a, l1b, l1c to l48a, ...... control data for ch setti ngs of pwm circuits that adjust brightness of led l48b, l48c ? pf0 to pf3 ............................ control data for setting of the frame frequency of led driver output waveform ? lt1 to lt48 ......................... display data for led ? w10 to w16, w20 to w26, ... pwm data of pwm circuits of led driver output w30 to w36, w40 to w46, w50 to w56, w60 to w66 w70 to w76 b1 b0 d2 d1 1 1 0 oc di cl ce 1 0 0 0 0 0 1 b3 b2 a1 a0 a3 a2 0 0 0 0 0 0 bu sc fc2 fc1 1 0 0 fc0 0 fc3 dt0 dt1 0 d73 d74 d72 d71 d70 b1 b0 l1b l1a 1 1 l46c 0 pf3 1 0 0 l47c 0 0 1 b3 b2 a1 a0 a3 a2 l47a l48b l48a l48c pf2 pf0 0 0 0 0 1 0 1 0 pf1 0 0 0 l47b l45c l46a l46b l45b l45a w65 w64 w54 w52 w56 w55 w60 w63 w61 w76 w75 w71 w70 0 1 1 w66 w62 w72 w73 w74 w53 b1 b0 lt2 lt1 1 1 0... w22 w21 1 0 0 w11 0 0 1 b3 b2 a1 a0 a3 a2 0 w13 w12 w14 w20 w15 w33 w32 w25 w24 w36 w35 w34 w23 w16 w26 w30 w31 w10 0 lt48 lt47 w51 w50 w46 w45 w44 w43 w42 w41 w40 dd 3 bits
LC75805PE www.onsemi.com 13 control data 19 bits ccb address 8 bits display data for lcd 74 bits dd 3 bits fixed data 9 bits ccb address 8 bits control data 148 bits control data 49 bits ccb address 8 bits display data for led 48 bits fixed data 12 bits dd 3 bits (2) when cl is stopped at the high level (note 1) the input of serial data is taken in at the rising edge of cl, and latched at the falling edge of ce. in addition, this ic has the function that counts the number of cl cloc k to receive the correct serial data. that is to say, because it isn?t latched at the falling edge of ce when th e number of the count of cl in each serial data is wrong, receiving wrong serial data can be prevented. (note 2) dd ? ? ? direction data ? ccb address ......................... ?87h? ? d1 to d74 ............................. di splay data for lcd ? oc ........................................ control data for switch of internal oscillator operating mode and external clock operating mode ? fc0 to fc3 ........................... control data for setting of the frame frequency of common and segment output waveform ? dt0, dt1 ............................. control data for setting of dr ive scheme (setting of 1/1 to 1/4 duty drive scheme) of lcd ? sc ......................................... c ontrol data for turning on/off segments ? bu ........................................ cont rol data for switch of normal mode and power-saving mode ? l1a, l1b, l1c to l48a, ...... control data for ch setti ngs of pwm circuits that adjust brightness of led l48b, l48c ? pf0 to pf3 ............................ control data for setting of the frame frequency of led driver output waveform ? lt1 to lt48 ......................... display data for led ? w10 to w16, w20 to w26, ... pwm data of pwm circuits of led driver output w30 to w36, w40 to w46, w50 to w56, w60 to w66 w70 to w76 b1 b0 d2 d1 1 1 0 oc di cl ce 1 0 0 0 0 0 1 b3 b2 a1 a0 a3 a2 0 0 0 0 0 0 bu sc fc2 fc1 1 0 0 fc0 0 fc3 dt0 dt1 0 d73 d74 d72 d71 d70 b1 b0 l1b l1a 1 1 l46c 0 pf3 1 0 0 l47c 0 0 1 b3 b2 a1 a0 a3 a2 l47a l48b l48a l48c pf2 pf0 0 0 0 0 1 0 1 0 pf1 0 0 0 l47b l45c l46a l46b l45b l45a w65 w64 w54 w52 w56 w55 w60 w63 w61 w76 w75 w71 w70 0 1 1 w66 w62 w72 w73 w74 w53 b1 b0 lt2 lt1 1 1 0... w22 w21 1 0 0 w11 0 0 1 b3 b2 a1 a0 a3 a2 0 w13 w12 w14 w20 w15 w33 w32 w25 w24 w36 w35 w34 w23 w16 w26 w30 w31 w10 0 lt48 lt47 w51 w50 w46 w45 w44 w43 w42 w41 w40 dd 3 bits
LC75805PE www.onsemi.com 14 control data 23 bits ccb address 8 bits display data for lcd 38 bits dd 3 bits fixed data 9 bits ccb address 8 bits control data 148 bits control data 49 bits ccb address 8 bits display data for led 48 bits fixed data 12 bits dd 3 bits static drive (1/1 duty drive) (1) when cl is stopped at the low level (note 1) the input of serial data is taken in at the rising edge of cl, and latched at the falling edge of ce. in addition, this ic has the function that counts the number of cl cloc k to receive the correct serial data. that is to say, because it isn?t latched at the falling edge of ce when th e number of the count of cl in each serial data is wrong, receiving wrong serial data can be prevented. (note 2) dd ? ? ? direction data ? ccb address ......................... ?87h? ? d1 to d38 ............................. di splay data for lcd ? oc ........................................ control data for switch of internal oscillator operating mode and external clock operating mode ? fc0 to fc3 ........................... control data for setting of the frame frequency of common and segment output waveform ? dt0, dt1 ............................. control data for setting of dr ive scheme (setting of 1/1 to 1/4 duty drive scheme) of lcd ? sc ......................................... c ontrol data for turning on/off segments ? bu ........................................ cont rol data for switch of normal mode and power-saving mode ? l1a, l1b, l1c to l48a, ...... control data for ch setti ngs of pwm circuits that adjust brightness of led l48b, l48c ? pf0 to pf3 ............................ control data for setting of the frame frequency of led driver output waveform ? lt1 to lt48 ......................... display data for led ? w10 to w16, w20 to w26, ... pwm data of pwm circuits of led driver output w30 to w36, w40 to w46, w50 to w56, w60 to w66 w70 to w76 b1 b0 d2 d1 1 1 0 oc di cl ce 1 0 0 0 0 0 1 b3 b2 a1 a0 a3 a2 0 0 0 0 0 0 bu sc fc2 fc1 1 0 0 fc0 0 fc3 dt0 dt1 0 0 0 0 0 d38 b1 b0 l1b l1a 1 1 l46c 0 pf3 1 0 0 l47c 0 0 1 b3 b2 a1 a0 a3 a2 l47a l48b l48a l48c pf2 pf0 0 0 0 0 1 0 1 0 pf1 0 0 0 l47b l45c l46a l46b l45b l45a w65 w64 w54 w52 w56 w55 w60 w63 w61 w76 w75 w71 w70 0 1 1 w66 w62 w72 w73 w74 w53 b1 b0 lt2 lt1 1 1 0... w22 w21 1 0 0 w11 0 0 1 b3 b2 a1 a0 a3 a2 0 w13 w12 w14 w20 w15 w33 w32 w25 w24 w36 w35 w34 w23 w16 w26 w30 w31 w10 0 lt48 lt47 w51 w50 w46 w45 w44 w43 w42 w41 w40 dd 3 bits
LC75805PE www.onsemi.com 15 control data 23 bits ccb address 8 bits display data for lcd 38 bits dd 3 bits fixed data 9 bits ccb address 8 bits control data 148 bits control data 49 bits ccb address 8 bits display data for led 48 bits fixed data 12 bits dd 3 bits (2) when cl is stopped at the high level (note 1) the input of serial data is taken in at the rising edge of cl, and latched at the falling edge of ce. in addition, this ic has the function that counts the number of cl cloc k to receive the correct serial data. that is to say, because it isn?t latched at the falling edge of ce when th e number of the count of cl in each serial data is wrong, receiving wrong serial data can be prevented. (note 2) dd ? ? ? direction data ? ccb address ......................... ?87h? ? d1 to d38 ............................. di splay data for lcd ? oc ........................................ control data for switch of internal oscillator operating mode and external clock operating mode ? fc0 to fc3 ........................... control data for setting of the frame frequency of common and segment output waveform ? dt0, dt1 ............................. control data for setting of dr ive scheme (setting of 1/1 to 1/4 duty drive scheme) of lcd ? sc ......................................... c ontrol data for turning on/off segments ? bu ........................................ cont rol data for switch of normal mode and power-saving mode ? l1a, l1b, l1c to l48a, ...... control data for ch setti ngs of pwm circuits that adjust brightness of led l48b, l48c ? pf0 to pf3 ............................ control data for setting of the frame frequency of led driver output waveform ? lt1 to lt48 ......................... display data for led ? w10 to w16, w20 to w26, ... pwm data of pwm circuits of led driver output w30 to w36, w40 to w46, w50 to w56, w60 to w66 w70 to w76 b1 b0 d2 d1 1 1 0 oc di cl ce 1 0 0 0 0 0 1 b3 b2 a1 a0 a3 a2 0 0 0 0 0 0 bu sc fc2 fc1 1 0 0 fc0 0 fc3 dt0 dt1 0 0 0 0 0 d38 b1 b0 l1b l1a 1 1 l46c 0 pf3 1 0 0 l47c 0 0 1 b3 b2 a1 a0 a3 a2 l47a l48b l48a l48c pf2 pf0 0 0 0 0 1 0 1 0 pf1 0 0 0 l47b l45c l46a l46b l45b l45a w65 w64 w54 w52 w56 w55 w60 w63 w61 w76 w75 w71 w70 0 1 1 w66 w62 w72 w73 w74 w53 b1 b0 lt2 lt1 1 1 0... w22 w21 1 0 0 w11 0 0 1 b3 b2 a1 a0 a3 a2 0 w13 w12 w14 w20 w15 w33 w32 w25 w24 w36 w35 w34 w23 w16 w26 w30 w31 w10 0 lt48 lt47 w51 w50 w46 w45 w44 w43 w42 w41 w40 dd 3 bits
LC75805PE www.onsemi.com 16 control data functions (1) oc ? control data for switch of internal oscillator operating mode and external clock operating mode this control data bit selects either the internal oscillator operating mode or external clock operating mode. oc fundamental cloc k operating mode input pin (osci) state 0 internal oscillator operating mode connect to gnd 1 external clock operating mode input the clock (f ck = 100 to 600 [khz]) from the outside (2) fc0 to fc3 ? control data for setting of the frame frequency of common and segment output waveform these control data bits set the frame frequency of common and segment output waveform. fc0 fc1 fc2 fc3 frame frequency of common and se gment output waveform fo [hz] internal oscillator operating mode (control data oc =?0?, fosc = 300 [khz] typ) external clock operating mode (control data oc =?1?, f ck = 300 [khz] typ) 0 0 0 0 fosc/4992 f ck /4992 1 0 0 0 fosc/4608 f ck /4608 0 1 0 0 fosc/4224 f ck /4224 1 1 0 0 fosc/3840 f ck /3840 0 0 1 0 fosc/3456 f ck /3456 1 0 1 0 fosc/3072 f ck /3072 0 1 1 0 fosc/2688 f ck /2688 1 1 1 0 fosc/2496 f ck /2496 0 0 0 1 fosc/2448 f ck /2448 1 0 0 1 fosc/2304 f ck /2304 0 1 0 1 fosc/2112 f ck /2112 1 1 0 1 fosc/1920 f ck /1920 0 0 1 1 fosc/1728 f ck /1728 1 0 1 1 fosc/1536 f ck /1536 0 1 1 1 fosc/1344 f ck /1344 1 1 1 1 fosc/1152 f ck /1152 (3) dt0, dt1 ? control data for setting of drive scheme (setting of 1/1 to 1/4 duty drive scheme) of lcd these control bits select 1/4-duty 1/3-bias drive, 1/3-duty 1/3-bias drive, 1/2-duty 1/2-bias drive, or static drive (1/1-duty drive) of lcd. dt0 dt1 drive scheme for lcd each pin state com2/s38 com3/s37 com4/s36 0 0 1/4-duty 1/3-bias drive com2 com3 com4 1 0 1/3-duty 1/3-bias drive com2 com3 s36 0 1 1/2-duty 1/2-bias drive com2 s37 s36 1 1 static drive (1/1-duty drive) s38 s37 s36 note) com2 to com4: common output / s38 to s36: segment output (4) sc ? control data for turning on/off segments this control data bit controls the on/off state of the segments. sc display state 0 on 1 off note that when the segments are turned off by setting sc to 1, the segments are turning off by outputting segment off waveforms from the segment output pins.
LC75805PE www.onsemi.com 17 (5) bu ? control data for switch of normal mode and power-saving mode this control data bit selects either normal mode or power-saving mode. bu mode 0 normal mode 1 power-saving mode the oscillation of internal oscillator circuit is stopped when in ternal oscillator operating mode (oc = [0]), and the receiving of external clock isn?t admitted when external clock operating mode (oc = [1]). in addition, common and segment output pins are v ss level, and led driver output pins are high impedance. (6) l1a, l1b, l1c to l48a, l48b, l48c ? control data for ch settings of pwm circuits that adjust brightness of led these control data bits set the ch of pwm circuit for led driver output pins, ld1 to ld48. lna lnb lnc ch of pwm circuit for led driver output ldn 0 0 0 pwm circuit is not selected. (the setting of turning on/off of the duty 100% by display data ltn for led is possible.) 1 0 0 pwm circuit (ch1) is selected. 0 1 0 pwm circuit (ch2) is selected. 1 1 0 pwm circuit (ch3) is selected. 0 0 1 pwm circuit (ch4) is selected. 1 0 1 pwm circuit (ch5) is selected. 0 1 1 pwm circuit (ch6) is selected. 1 1 1 pwm circuit (ch7) is selected. note) lna, lnb, lnc (n = 1 to 48) data are control data that set the ch of pwm circuit for led driver output pins ldn (n = 1 to 48). for example, if (l1a, l1b, l1c) = (1, 0, 0), (l11a, l11b, l11c) = (1, 1, 0) and (l21a, l21b, l21c) = (0, 1, 1) is set, led driver output pin ld1 select pwm circuit (ch1) and led driver output pin ld11 select pwm circuit (ch3) and led driver output pin ld21 select pwm circuit (ch6). (7) pf0 to pf3 ? control data for setting of the frame frequency of led driver output waveform these control data bits set the frame frequency of le d driver output waveform of led output pin setting pwm circuit (ch1 to ch7). pf0 pf1 pf2 pf3 frame frequency of led driver output waveform fp [hz] internal oscillator operating mode (control data oc =?0?, fosc = 300 [khz] typ) external clock operating mode (control data oc =?1?, f ck = 300 [khz] typ) 0 0 0 0 fosc/1664 f ck /1664 1 0 0 0 fosc/1536 f ck /1536 0 1 0 0 fosc/1408 f ck /1408 1 1 0 0 fosc/1280 f ck /1280 0 0 1 0 fosc/1152 f ck /1152 1 0 1 0 fosc/1024 f ck /1024 0 1 1 0 fosc/896 f ck /896 1 1 1 0 fosc/768 f ck /768 0 0 0 1 fosc/640 f ck /640 1 0 0 1 fosc/512 f ck /512 note) if (pf0, pf1, pf2, pf3) = (x, 1, 0, 1), (x, x, 1, 1) are set, the frame frequency (fosc/1408, fck/1408) of setting (pf0, pf1, pf2, pf3) = (0, 1, 0, 0) is selected.
LC75805PE www.onsemi.com 18 (8) w10 to w16, w20 to w26, w30 to w36, w40 to w46, w50 to w56, w60 to w66, w70 to w76 ? pwm data of pwm circuit for led driver output these control data bits set led lighting time per 1 frame of led driver output waveform of led driver output pin setting pwm circuit (ch1 to ch7). wn0 wn1 wn2 wn3 wn4 wn5 wn6 led lighting time per 1 frame wn0 wn1 wn2 wn3 wn4 wn5 wn6 led lighting time per 1 frame 0 0 0 0 0 0 0 (1/128) ? tp 0 0 0 0 0 0 1 (65/128) ? tp 1 0 0 0 0 0 0 (2/128) ? tp 1 0 0 0 0 0 1 (66/128) ? tp 0 1 0 0 0 0 0 (3/128) ? tp 0 1 0 0 0 0 1 (67/128) ? tp 1 1 0 0 0 0 0 (4/128) ? tp 1 1 0 0 0 0 1 (68/128) ? tp 0 0 1 0 0 0 0 (5/128) ? tp 0 0 1 0 0 0 1 (69/128) ? tp 1 0 1 0 0 0 0 (6/128) ? tp 1 0 1 0 0 0 1 (70/128) ? tp 0 1 1 0 0 0 0 (7/128) ? tp 0 1 1 0 0 0 1 (71/128) ? tp 1 1 1 0 0 0 0 (8/128) ? tp 1 1 1 0 0 0 1 (72/128) ? tp 0 0 0 1 0 0 0 (9/128) ? tp 0 0 0 1 0 0 1 (73/128) ? tp 1 0 0 1 0 0 0 (10/128) ? tp 1 0 0 1 0 0 1 (74/128) ? tp 0 1 0 1 0 0 0 (11/128) ? tp 0 1 0 1 0 0 1 (75/128) ? tp 1 1 0 1 0 0 0 (12/128) ? tp 1 1 0 1 0 0 1 (76/128) ? tp 0 0 1 1 0 0 0 (13/128) ? tp 0 0 1 1 0 0 1 (77/128) ? tp 1 0 1 1 0 0 0 (14/128) ? tp 1 0 1 1 0 0 1 (78/128) ? tp 0 1 1 1 0 0 0 (15/128) ? tp 0 1 1 1 0 0 1 (79/128) ? tp 1 1 1 1 0 0 0 (16/128) ? tp 1 1 1 1 0 0 1 (80/128) ? tp 0 0 0 0 1 0 0 (17/128) ? tp 0 0 0 0 1 0 1 (81/128) ? tp 1 0 0 0 1 0 0 (18/128) ? tp 1 0 0 0 1 0 1 (82/128) ? tp 0 1 0 0 1 0 0 (19/128) ? tp 0 1 0 0 1 0 1 (83/128) ? tp 1 1 0 0 1 0 0 (20/128) ? tp 1 1 0 0 1 0 1 (84/128) ? tp 0 0 1 0 1 0 0 (21/128) ? tp 0 0 1 0 1 0 1 (85/128) ? tp 1 0 1 0 1 0 0 (22/128) ? tp 1 0 1 0 1 0 1 (86/128) ? tp 0 1 1 0 1 0 0 (23/128) ? tp 0 1 1 0 1 0 1 (87/128) ? tp 1 1 1 0 1 0 0 (24/128) ? tp 1 1 1 0 1 0 1 (88/128) ? tp 0 0 0 1 1 0 0 (25/128) ? tp 0 0 0 1 1 0 1 (89/128) ? tp 1 0 0 1 1 0 0 (26/128) ? tp 1 0 0 1 1 0 1 (90/128) ? tp 0 1 0 1 1 0 0 (27/128) ? tp 0 1 0 1 1 0 1 (91/128) ? tp 1 1 0 1 1 0 0 (28/128) ? tp 1 1 0 1 1 0 1 (92/128) ? tp 0 0 1 1 1 0 0 (29/128) ? tp 0 0 1 1 1 0 1 (93/128) ? tp 1 0 1 1 1 0 0 (30/128) ? tp 1 0 1 1 1 0 1 (94/128) ? tp 0 1 1 1 1 0 0 (31/128) ? tp 0 1 1 1 1 0 1 (95/128) ? tp 1 1 1 1 1 0 0 (32/128) ? tp 1 1 1 1 1 0 1 (96/128) ? tp 0 0 0 0 0 1 0 (33/128) ? tp 0 0 0 0 0 1 1 (97/128) ? tp 1 0 0 0 0 1 0 (34/128) ? tp 1 0 0 0 0 1 1 (98/128) ? tp 0 1 0 0 0 1 0 (35/128) ? tp 0 1 0 0 0 1 1 (99/128) ? tp 1 1 0 0 0 1 0 (36/128) ? tp 1 1 0 0 0 1 1 (100/128) ? tp 0 0 1 0 0 1 0 (37/128) ? tp 0 0 1 0 0 1 1 (101/128) ? tp 1 0 1 0 0 1 0 (38/128) ? tp 1 0 1 0 0 1 1 (102/128) ? tp 0 1 1 0 0 1 0 (39/128) ? tp 0 1 1 0 0 1 1 (103/128) ? tp 1 1 1 0 0 1 0 (40/128) ? tp 1 1 1 0 0 1 1 (104/128) ? tp 0 0 0 1 0 1 0 (41/128) ? tp 0 0 0 1 0 1 1 (105/128) ? tp 1 0 0 1 0 1 0 (42/128) ? tp 1 0 0 1 0 1 1 (106/128) ? tp 0 1 0 1 0 1 0 (43/128) ? tp 0 1 0 1 0 1 1 (107/128) ? tp 1 1 0 1 0 1 0 (44/128) ? tp 1 1 0 1 0 1 1 (108/128) ? tp 0 0 1 1 0 1 0 (45/128) ? tp 0 0 1 1 0 1 1 (109/128) ? tp 1 0 1 1 0 1 0 (46/128) ? tp 1 0 1 1 0 1 1 (110/128) ? tp 0 1 1 1 0 1 0 (47/128) ? tp 0 1 1 1 0 1 1 (111/128) ? tp 1 1 1 1 0 1 0 (48/128) ? tp 1 1 1 1 0 1 1 (112/128) ? tp 0 0 0 0 1 1 0 (49/128) ? tp 0 0 0 0 1 1 1 (113/128) ? tp 1 0 0 0 1 1 0 (50/128) ? tp 1 0 0 0 1 1 1 (114/128) ? tp 0 1 0 0 1 1 0 (51/128) ? tp 0 1 0 0 1 1 1 (115/128) ? tp 1 1 0 0 1 1 0 (52/128) ? tp 1 1 0 0 1 1 1 (116/128) ? tp 0 0 1 0 1 1 0 (53/128) ? tp 0 0 1 0 1 1 1 (117/128) ? tp 1 0 1 0 1 1 0 (54/128) ? tp 1 0 1 0 1 1 1 (118/128) ? tp 0 1 1 0 1 1 0 (55/128) ? tp 0 1 1 0 1 1 1 (119/128) ? tp 1 1 1 0 1 1 0 (56/128) ? tp 1 1 1 0 1 1 1 (120/128) ? tp 0 0 0 1 1 1 0 (57/128) ? tp 0 0 0 1 1 1 1 (121/128) ? tp 1 0 0 1 1 1 0 (58/128) ? tp 1 0 0 1 1 1 1 (122/128) ? tp 0 1 0 1 1 1 0 (59/128) ? tp 0 1 0 1 1 1 1 (123/128) ? tp 1 1 0 1 1 1 0 (60/128) ? tp 1 1 0 1 1 1 1 (124/128) ? tp 0 0 1 1 1 1 0 (61/128) ? tp 0 0 1 1 1 1 1 (125/128) ? tp 1 0 1 1 1 1 0 (62/128) ? tp 1 0 1 1 1 1 1 (126/128) ? tp 0 1 1 1 1 1 0 (63/128) ? tp 0 1 1 1 1 1 1 (127/128) ? tp 1 1 1 1 1 1 0 (64/128) ? tp 1 1 1 1 1 1 1 (128/128) ? tp note) w10 to w16 : pwm data of pwm circuit (ch1) / w20 to w26 : pwm data of pwm circuit (ch2) w30 to w36 : pwm data of pwm circuit (ch3) / w40 to w46 : pwm data of pwm circuit (ch4) w50 to w56 : pwm data of pwm circuit (ch5) / w60 to w66 : pwm data of pwm circuit (ch6) w70 to w76 : pwm data of pwm circuit (ch7) 1 f p tp=
LC75805PE www.onsemi.com 19 descriptions of display data for lcd (1) correspondence of output pins to display data for lcd at 1/4 duty drive output pin com1 com2 co m3 com4 output pin com1 com2 com3 com4 s1 d1 d2 d3 d4 s19 d73 d74 d75 d76 s2 d5 d6 d7 d8 s20 d77 d78 d79 d80 s3 d9 d10 d11 d12 s21 d81 d82 d83 d84 s4 d13 d14 d15 d16 s22 d85 d86 d87 d88 s5 d17 d18 d19 d20 s23 d89 d90 d91 d92 s6 d21 d22 d23 d24 s24 d93 d94 d95 d96 s7 d25 d26 d27 d28 s25 d97 d98 d99 d100 s8 d29 d30 d31 d32 s26 d101 d102 d103 d104 s9 d33 d34 d35 d36 s27 d105 d106 d107 d108 s10 d37 d38 d39 d40 s28 d109 d110 d111 d112 s11 d41 d42 d43 d44 s29 d113 d114 d115 d116 s12 d45 d46 d47 d48 s30 d117 d118 d119 d120 s13 d49 d50 d51 d52 s31 d121 d122 d123 d124 s14 d53 d54 d55 d56 s32 d125 d126 d127 d128 s15 d57 d58 d59 d60 s33 d129 d130 d131 d132 s16 d61 d62 d63 d64 s34 d133 d134 d135 d136 s17 d65 d66 d67 d68 s35 d137 d138 d139 d140 s18 d69 d70 d71 d72 for example, the table below lists the output states for the s21 output pin. display data output pin (s21) state d81 d82 d83 d84 0 0 0 0 the lcd segments corresponding to com1, com2, com3 and com4 are off. 0 0 0 1 the lcd segment corresponding to com4 is on. 0 0 1 0 the lcd segment corresponding to com3 is on. 0 0 1 1 the lcd segments corresponding to com3 and com4 are on. 0 1 0 0 the lcd segment corresponding to com2 is on. 0 1 0 1 the lcd segments corresponding to com2 and com4 are on. 0 1 1 0 the lcd segments corresponding to com2 and com3 are on. 0 1 1 1 the lcd segments corresponding to com2, com3 and com4 are on. 1 0 0 0 the lcd segment corresponding to com1 is on. 1 0 0 1 the lcd segments corresponding to com1 and com4 are on. 1 0 1 0 the lcd segments corresponding to com1 and com3 are on. 1 0 1 1 the lcd segments corresponding to com1, com3 and com4 are on. 1 1 0 0 the lcd segments corresponding to com1 and com2 are on. 1 1 0 1 the lcd segments corresponding to com1, com2 and com4 are on. 1 1 1 0 the lcd segments corresponding to com1, com2 and com3 are on. 1 1 1 1 the lcd segments corresponding to com1, com2, com3 and com4 are on.
LC75805PE www.onsemi.com 20 (2) correspondence of output pins to display data for lcd at 1/3 duty drive output pin com1 com2 com3 output pi n com1 com2 com3 s1 d1 d2 d3 s20 d58 d59 d60 s2 d4 d5 d6 s21 d61 d62 d63 s3 d7 d8 d9 s22 d64 d65 d66 s4 d10 d11 d12 s23 d67 d68 d69 s5 d13 d14 d15 s24 d70 d71 d72 s6 d16 d17 d18 s25 d73 d74 d75 s7 d19 d20 d21 s26 d76 d77 d78 s8 d22 d23 d24 s27 d79 d80 d81 s9 d25 d26 d27 s28 d82 d83 d84 s10 d28 d29 d30 s29 d85 d86 d87 s11 d31 d32 d33 s30 d88 d89 d90 s12 d34 d35 d36 s31 d91 d92 d93 s13 d37 d38 d39 s32 d94 d95 d96 s14 d40 d41 d42 s33 d97 d98 d99 s15 d43 d44 d45 s34 d100 d101 d102 s16 d46 d47 d48 s35 d103 d104 d105 s17 d49 d50 d51 s36/com4 d106 d107 d108 s18 d52 d53 d54 s19 d55 d56 d57 note) s36/com4 pin is selected segment output. for example, the table below lists the output states for the s21 output pin. display data output pin (s21) state d61 d62 d63 0 0 0 the lcd segments corresponding to com1, com2 and com3 are off. 0 0 1 the lcd segment corresponding to com3 is on. 0 1 0 the lcd segment corresponding to com2 is on. 0 1 1 the lcd segments corresponding to com2 and com3 are on. 1 0 0 the lcd segment corresponding to com1 is on. 1 0 1 the lcd segments corresponding to com1 and com3 are on. 1 1 0 the lcd segments corresponding to com1 and com2 are on. 1 1 1 the lcd segments corresponding to com1, com2 and com3 are on.
LC75805PE www.onsemi.com 21 (3) correspondence of output pins to display data for lcd at 1/2 duty drive output pin com1 com2 output pin com1 com2 s1 d1 d2 s20 d39 d40 s2 d3 d4 s21 d41 d42 s3 d5 d6 s22 d43 d44 s4 d7 d8 s23 d45 d46 s5 d9 d10 s24 d47 d48 s6 d11 d12 s25 d49 d50 s7 d13 d14 s26 d51 d52 s8 d15 d16 s27 d53 d54 s9 d17 d18 s28 d55 d56 s10 d19 d20 s29 d57 d58 s11 d21 d22 s30 d59 d60 s12 d23 d24 s31 d61 d62 s13 d25 d26 s32 d63 d64 s14 d27 d28 s33 d65 d66 s15 d29 d30 s34 d67 d68 s16 d31 d32 s35 d69 d70 s17 d33 d34 s36/com4 d71 d72 s18 d35 d36 s37/com3 d73 d74 s19 d37 d38 note) s36/com4 and s37/com3 pins are selected segment output. for example, the table below lists the output states for the s21 output pin. display data output pin (s21) state d41 d42 0 0 the lcd segments corresponding to com1 and com2 are off. 0 1 the lcd segment corresponding to com2 is on. 1 0 the lcd segment corresponding to com1 is on. 1 1 the lcd segment corresponding to com1 and com2 are on.
LC75805PE www.onsemi.com 22 (4) correspondence of output pins to display da ta for lcd at static drive (1/1 duty drive) output pin com1 output pin com1 s1 d1 s21 d21 s2 d2 s22 d22 s3 d3 s23 d23 s4 d4 s24 d24 s5 d5 s25 d25 s6 d6 s26 d26 s7 d7 s27 d27 s8 d8 s28 d28 s9 d9 s29 d29 s10 d10 s30 d30 s11 d11 s31 d31 s12 d12 s32 d32 s13 d13 s33 d33 s14 d14 s34 d34 s15 d15 s35 d35 s16 d16 s36/com4 d36 s17 d17 s37/com3 d37 s18 d18 s38/com2 d38 s19 d19 s20 d20 note) s36/com4, s37/com3 and s38/com2 pins are selected segment output. for example, the table below lists the output states for the s21 output pin. display data output pin (s21) state d21 0 the lcd segment to com1 is off. 1 the lcd segment to com1 is on.
LC75805PE www.onsemi.com 23 correspondence of output pins to display data for led output pin display data output pin display data ld1 lt1 ld25 lt25 ld2 lt2 ld26 lt26 ld3 lt3 ld27 lt27 ld4 lt4 ld28 lt28 ld5 lt5 ld29 lt29 ld6 lt6 ld30 lt30 ld7 lt7 ld31 lt31 ld8 lt8 ld32 lt32 ld9 lt9 ld33 lt33 ld10 lt10 ld34 lt34 ld11 lt11 ld35 lt35 ld12 lt12 ld36 lt36 ld13 lt13 ld37 lt37 ld14 lt14 ld38 lt38 ld15 lt15 ld39 lt39 ld16 lt16 ld40 lt40 ld17 lt17 ld41 lt41 ld18 lt18 ld42 lt42 ld19 lt19 ld43 lt43 ld20 lt20 ld44 lt44 ld21 lt21 ld45 lt45 ld22 lt22 ld46 lt46 ld23 lt23 ld47 lt47 ld24 lt24 ld48 lt48 for example, the table below lists the output states for the ld21 output pin. display data output pin (ld21) state lt21 0 led is off. (high impedance output) 1 led is on. note) if (l21a, l21b, l21c) = (0, 0, 0) is set, the led by 100% duty is on. if (l21a, l21b, l21c) = (1, 0, 0) is set, th e led depending on the contents of pwm data, w10 to w16, of pwm circuit (ch1) is on. if (l21a, l21b, l21c) = (0, 1, 0) is set, th e led depending on the contents of pwm data, w20 to w26, of pwm circuit (ch2) is on. if (l21a, l21b, l21c) = (1, 1, 0) is set, th e led depending on the contents of pwm data, w30 to w36, of pwm circuit (ch3) is on. if (l21a, l21b, l21c) = (0, 0, 1) is set, th e led depending on the contents of pwm data, w40 to w46, of pwm circuit (ch4) is on. if (l21a, l21b, l21c) = (1, 0, 1) is set, th e led depending on the contents of pwm data, w50 to w56, of pwm circuit (ch5) is on. if (l21a, l21b, l21c) = (0, 1, 1) is set, th e led depending on the contents of pwm data, w60 to w66, of pwm circuit (ch6) is on. if (l21a, l21b, l21c) = (1, 1, 1) is set, th e led depending on the contents of pwm data, w70 to w76, of pwm circuit (ch7) is on.
LC75805PE www.onsemi.com 24 lcd drive waveform (1/4-duty 1/3-bias drive, frame inversion drive) 2/3v dd 1/3v dd fo [hz] v dd com3 com2 com1 com4 lcd driver output when all lcd segments corresponding to com1, com2, com3 and com4 are on. lcd driver output when lcd segments corresponding to com2 and com4 are on. lcd driver output when only lcd segments corresponding to com4 are on. lcd driver output when lcd segments corresponding to com1, com2 and com3 are on. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when only lcd segments corresponding to com1 are on. lcd driver output when all lcd segments corresponding to com1, com2, com3 and com4 are off. 0v 2/3v dd 1/3v dd v dd 0v 2/3v dd 1/3v dd v dd 0v 2/3v dd 1/3v dd v dd 0v 2/3v dd 1/3v dd v dd 0v 2/3v dd 1/3v dd v dd 0v 2/3v dd 1/3v dd v dd 0v 2/3v dd 1/3v dd v dd 0v 2/3v dd 1/3v dd v dd 0v 2/3v dd 1/3v dd v dd 0v 2/3v dd 1/3v dd v dd 0v 2/3v dd 1/3v dd v dd 0v 2/3v dd 1/3v dd v dd 0v 2/3v dd 1/3v dd v dd 0v 2/3v dd v dd 1/3v dd 0v
LC75805PE www.onsemi.com 25 lcd drive waveform (1/3-duty 1/3-bias drive, frame inversion drive) com3 com2 com1 lcd driver output when all lcd segments corresponding to com1, com2 and com3 are on. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when only lcd segments corresponding to com1 are on. lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. lcd driver output when all lcd segments corresponding to com1, com2 and com3 are off. 1/3v dd 2/3v dd v dd 0v 1/3v dd 2/3v dd v dd 0v 1/3v dd 2/3v dd v dd 0v 1/3v dd 2/3v dd v dd 0v 1/3v dd 2/3v dd v dd 0v 1/3v dd 2/3v dd v dd 0v 1/3v dd 2/3v dd v dd 0v 1/3v dd 2/3v dd v dd 0v 1/3v dd 2/3v dd v dd 0v 1/3v dd 2/3v dd v dd 0v v dd fo [hz] 1/3v dd 2/3v dd 0v
LC75805PE www.onsemi.com 26 lcd drive waveform (1/2-duty 1/2-bi as drive, frame inversion drive) lcd drive waveform (static drive) fc0 fc1 fc2 fc3 frame frequency of common and se gment output waveform fo [hz] internal oscillator operating mode (control data oc = ?0?, fosc = 300 [khz] typ) external clock operating mode (control data oc = ?1?, f ck = 300 [khz] typ) 0 0 0 0 fosc/4992 f ck /4992 1 0 0 0 fosc/4608 f ck /4608 0 1 0 0 fosc/4224 f ck /4224 1 1 0 0 fosc/3840 f ck /3840 0 0 1 0 fosc/3456 f ck /3456 1 0 1 0 fosc/3072 f ck /3072 0 1 1 0 fosc/2688 f ck /2688 1 1 1 0 fosc/2496 f ck /2496 0 0 0 1 fosc/2448 f ck /2448 1 0 0 1 fosc/2304 f ck /2304 0 1 0 1 fosc/2112 f ck /2112 1 1 0 1 fosc/1920 f ck /1920 0 0 1 1 fosc/1728 f ck /1728 1 0 1 1 fosc/1536 f ck /1536 0 1 1 1 fosc/1344 f ck /1344 1 1 1 1 fosc/1152 f ck /1152 fo [hz] v dd 1/2v dd v ss v dd v ss v dd v ss v dd v ss com1 lcd driver output when all lcd segments corresponding to com1 and com2 are off. com2 lcd driver output when only lcd segments corresponding to com1 are on. lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when all lcd segments corresponding to com1 and com2 are on. 1/2v dd v ss v dd v ss v dd fo [hz] v dd v ss v dd v ss v dd v ss com1 lcd driver output when lcd segments are off. lcd driver output when lcd segments are on.
LC75805PE www.onsemi.com 27 led drive waveform lt1 to lt6 l1a to l6a l1b to l6b l1c to l6c w10 w11 w12 w13 w14 w15 w16 pwm (ch) 1 1 0 0 1 1 1 1 0 1 1 pwm ch1, (112/128) x tp lt7 to lt12 l7a to l12a l7b to l12b l7c to l12c w20 w21 w22 w23 w24 w25 w26 pwm (ch) 1 0 1 0 1 1 1 1 1 0 1 pwm ch2, (96/128) x tp lt13 to lt18 l13a to l18a l13b to l18b l13c to l18c w30 w31 w32 w33 w34 w35 w36 pwm (ch) 1 1 1 0 1 1 1 1 0 0 1 pwm ch3, (80/128) x tp lt19 to lt24 l19a to l24a l19b to l24b l19c to l24c w40 w41 w42 w43 w44 w45 w46 pwm (ch) 1 0 0 1 1 1 1 1 0 0 0 pwm ch4, (16/128) x tp lt25 to lt30 l25a to l30a l25b to l30b l25c to l30c w50 w51 w52 w53 w54 w55 w56 pwm (ch) 1 1 0 1 1 1 1 1 1 0 0 pwm ch5, (32/128) x tp lt31 to lt36 l31a to l36a l31b to l36b l31c to l36c w60 w61 w62 w63 w64 w65 w66 pwm (ch) 1 0 1 1 1 1 1 1 0 1 0 pwm ch6, (48/128) x tp lt37 to lt42 l37a to l42a l37b to l42b l37c to l42c w70 w71 w72 w73 w74 w75 w76 pwm (ch) 1 1 1 1 1 1 1 1 1 1 0 pwm ch7, (64/128) x tp lt43 to lt45 l43a to l45a l43b to l45b l43c to l45c pwm (ch) 0 0 0 0 no select pwm, turning off lt46 to lt48 l46a to l48a l46b to l48b l46c to l48c pwm (ch) 1 0 0 0 no select pwm, turning on 1 fp tp= (112/128) ? tp v oup v ss (96/128) ? tp v ss v oup (80/128) ? tp v ss v oup (64/128) ? tp v oup v ss v ss v oup v ss v oup (16/128) ? tp (16/128) ? tp v oup v ss (32/128) ? tp v ss v oup (48/128) ? tp ld1 to ld6 (pwm ch1) ld7 to ld12 (pwm ch2) ld13 to ld18 (pwm ch3) ld37 to ld42 (pwm ch7) ld43 to ld45 ld46 to ld48 ld19 to ld24 (pwm ch4) ld25 to ld30 (pwm ch5) ld31 to ld36 (pwm ch6) v ss v oup (32/128) ? tp (48/128) ? tp (64/128) ? tp tp tp (112/128) ? tp (96/128) ? tp (80/128) ? tp < lighting period > < lighting period > < lighting period > < lighting period > < continuous lights out > < continuous lighting > < lighting period > < lighting period > < lighting period >
LC75805PE www.onsemi.com 28 pf0 pf1 pf2 pf3 frame frequency of led driver output waveform fp [hz] internal oscillator operating mode (control data oc =?0?, fosc = 300 [khz] typ) external clock operating mode (control data oc =?1?, f ck = 300 [khz] typ) 0 0 0 0 fosc/1664 f ck /1664 1 0 0 0 fosc/1536 f ck /1536 0 1 0 0 fosc/1408 f ck /1408 1 1 0 0 fosc/1280 f ck /1280 0 0 1 0 fosc/1152 f ck /1152 1 0 1 0 fosc/1024 f ck /1024 0 1 1 0 fosc/896 f ck /896 1 1 1 0 fosc/768 f ck /768 0 0 0 1 fosc/640 f ck /640 1 0 0 1 fosc/512 f ck /512 note) if (pf0, pf1, pf2, pf3) = (x, 1, 0, 1) or (x, x, 1, 1) are set, frame frequency (fosc/1408, f ck /1408) of setting (pf0, pf1, pf2, pf3) = (0, 1, 0, 0) is selected.
LC75805PE www.onsemi.com 29 display control and the inh pin since the lsi internal data (1/4 duty drive: lcd display data d1 to d140 + led display data lt1 to lt48 + control data, 1/3 duty drive: lcd display data d1 to d108 + led display data lt1 to lt48 + control data, 1/2 duty drive: lcd display data d1 to d74 + led display data lt1 to lt48 + control data, static drive: lcd display data d1 to d38 + led display data lt1 to lt48 + control data) is undef ined when power is first applied, applications should set the inh pin low at the same time as power is applied to turn off the display of lcd and led (ld1 to ld48 ? ? ? high impedance, com1 and com2/s38 to com4/s36 and s35 to s1 ? ? ? vss level). the serial data is transferred from the controller during this period, and then input inh =?h? after the serial data is tr ansferred. this procedure prevents meaningless display at power on. (see [fig 4], [fig 5], [fig 6], [fig 7]) (1) 1/4 duty drive (2) 1/3 duty drive notes: t1 ? 10 ? s t2 ? 0 tc?10 ? s min v dd ce inh [fig 4] d1 to d140, oc, fc0 to fc3, dt0, dt1, sc, bu internal data internal data l1a, l1b, l1c to l48a, l48b, l48c, pf0 to pf3 internal data lt1 to lt48, w10 to w16, w20 to w26, w30 to w36, w40 to w46, w50 to w56, w60 to w66, w70 to w76 t1 display data for lcd, display data for led and control data transfer undefined defined undefined v il 1 tc v il 1 undefined defined undefined undefined defined undefined t2 notes: t1 ? 10 ? s t2 ? 0 tc?10 ? s min v dd ce inh [fig 5] d1 to d108, oc, fc0 to fc3, dt0, dt1, sc, bu internal data internal data l1a, l1b, l1c to l48a, l48b, l48c, pf0 to pf3 internal data lt1 to lt48, w10 to w16, w20 to w26, w30 to w36, w40 to w46, w50 to w56, w60 to w66, w70 to w76 t1 display data for lcd, display data for led and control data transfer undefined defined undefined v il 1 tc v il 1 undefined defined undefined undefined defined undefined t2
LC75805PE www.onsemi.com 30 (3) 1/2 duty drive (4) static drive (1/1 duty drive) notes: t1 ? 10 ? s t2 ? 0 tc?10 ? s min v dd ce inh [fig 6] d1 to d74, oc, fc0 to fc3, dt0, dt1, sc, bu internal data internal data l1a, l1b, l1c to l48a, l48b, l48c, pf0 to pf3 internal data lt1 to lt48, w10 to w16, w20 to w26, w30 to w36, w40 to w46, w50 to w56, w60 to w66, w70 to w76 t1 display data for lcd, display data for led and control data transfer undefined defined undefined v il 1 tc v il 1 undefined defined undefined undefined defined undefined t2 notes: t1 ? 10 ? s t2 ? 0 tc?10 ? s min v dd ce inh [fig 7] d1 to d38, oc, fc0 to fc3, dt0, dt1, sc, bu internal data internal data l1a, l1b, l1c to l48a, l48b, l48c, pf0 to pf3 internal data lt1 to lt48, w10 to w16, w20 to w26, w30 to w36, w40 to w46, w50 to w56, w60 to w66, w70 to w76 t1 display data for lcd, display data for led and control data transfer undefined defined undefined v il 1 tc v il 1 undefined defined undefined undefined defined undefined t2
LC75805PE www.onsemi.com 31 osci pin peripheral circuit (1) internal oscillator operating mode (control data oc = ?0?) connect osci pin to gnd if internal oscillator operating mode is selected. (2) external clock operating mode (control data oc = ?1?) input the external clock (f ck = 100 to 600 [khz]) to osci pin if external clock operating mode is selected. osci external clock output pin rg external oscillato r osci
LC75805PE www.onsemi.com 32 application circuit example 1 1/4-duty, 1/3-bias * 1 pins (ce, cl, di, inh ) connected to the controller are supported 5 v. * 2 external clock input pin osci is supported 5 v. connect to gnd at internal oscillator operating mode, and input the external clock (f ck = 100 to 600 [khz]) to osci pin at external clock operating mode. (see ?osci pin peripheral circuit?) * 3 load capacity of the lcd panel is recommended 9000 [pf] or less. application circuit example 2 1/3-duty, 1/3-bias * 1 pins (ce, cl, di, inh ) connected to the controller are supported 5 v. * 2 external clock input pin osci is supported 5 v. connect to gnd at internal oscillator operating mode, and input the external clock (f ck = 100 to 600 [khz]) to osci pin at external clock operating mode. (see ?osci pin peripheral circuit?) * 3 load capacity of the lcd panel is recommended 9000 [pf] or less. from the controller *1 di cl ce inh ld2 ld48 s1 s5 s34 s35 s37/com3 s38/com2 com1 lcd panel (display of up to 140 segments) *3 s36/com4 led power supply (12v) +5.0v v ss v dd ld47 ld3 ld1 s2 s3 s4 osci *2 external clock input v ss v ss v ss v ss v ss v ss from the controller *1 di cl ce inh ld2 ld48 s1 s5 s34 s35 s37/com3 s38/com2 com1 lcd panel (display of up to 108 segments) *3 com4/s36 led power supply (12v) +5.0v v ss v dd ld47 ld3 ld1 s2 s3 s4 osci *2 external clock input v ss v ss v ss v ss v ss v ss
LC75805PE www.onsemi.com 33 application circuit example 3 1/2-duty, 1/2-bias * 1 pins (ce, cl, di, inh ) connected to the controller are supported 5 v. * 2 external clock input pin osci is supported 5 v. connect to gnd at internal oscillator operating mode, and input the external clock (f ck = 100 to 600 [khz]) to osci pin at external clock operating mode. (see ?osci pin peripheral circuit?) * 3 load capacity of the lcd panel is recommended 9000 [pf] or less. application circuit example 4 static (1/1-duty) * 1 pins (ce, cl, di, inh ) connected to the controller are supported 5 v. * 2 external clock input pin osci is supported 5 v. connect to gnd at internal oscillator operating mode, and input the external clock (f ck = 100 to 600 [khz]) to osci pin at external clock operating mode. (see ?osci pin peripheral circuit?) * 3 load capacity of the lcd panel is recommended 9000 [pf] or less. from the controller *1 di cl ce inh ld2 ld48 s1 s5 s34 s35 com3/s37 s38/com2 com1 lcd panel (display of up to 74 segments) *3 com4/s36 led power supply (12v) +5.0v v ss v dd ld47 ld3 ld1 s2 s3 s4 osci *2 external clock input v ss v ss v ss v ss v ss v ss from the controller *1 di cl ce inh ld2 ld48 s1 s5 s34 s35 com3/s37 com2/s38 com1 lcd panel (display of up to 38 segments) *3 com4/s36 led power supply (12v) +5.0v v ss v dd ld47 ld3 ld1 s2 s3 s4 osci *2 external clock input v ss v ss v ss v ss v ss v ss
LC75805PE www.onsemi.com 34 on semiconductor and the on semiconductor logo are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries in the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and othe r intellectual property. a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does on semiconductor assume any liability arising out of the app lication or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, regulations and safety require ments or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the rights of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life sup port systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended fo r implantation in the human body. should buyer purchase or use on semiconductor products for any such unintended or unauthorized application, buyer sh all indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, d amages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resal e in any manner. ordering information device package shipping (qty / packing) LC75805PEh-3h qip100e(14x20) (pb-free / halogen free) 250 / tray foam LC75805PEs-3h qip100e(14x20) (pb-free / halogen free) 250 / tray foam

▲Up To Search▲

Price & Availability of LC75805PE

	To Download LC75805PE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .